The present invention is concerned with a method of fabrication of an electronic component, and with an electronic component as such. The invention is in particular (although not exclusively) applicable to transistor fabrication, and still more particularly to fabrication of thin film transistors.
Considerable research effort has been devoted in recent years to thin film transistors (TFTs), and particularly to TFTs utilizing bodies formed by thin films of semiconductor polymer. The TFTs so far proposed in the literature have been inverted horizontal structures. The gate is in most cases single crystal silicon which has been oxidized to produce a thin reliable oxide layer using a well defined technology, already available from work on silicon integrated circuits. An example of such a transistor is illustrated in schematic vertical section in FIG. 1, having a source 102 horizontally separated from a drain 104, both being formed above a gate 106 of silicon having an oxide layer 108 by which the gate is separated from the source and drain. The semiconductor body 110 is of polymer material.
A problem with the known horizontal TFT structures is that they have very large overlaps of the gate by the drain and source, as FIG. 1 clearly shows. In a typical inverter circuit, as used in digital applications, the drain voltage of the driver transistor is out of phase with that of the gate. This essentially doubles the magnitude of the voltage swing between these terminals. The same effect occurs with many devices used in this configuration. It is called the Miller Effect and essentially doubles the effective overlap capacitance. The gate channel capacitance is one unit of capacitance, the source is a second and the drain is two units, making a total of four. Without the overlap capacitances there would be only one unit of capacitance, and a circuit utilizing the transistor could go four times faster.
The silicon dioxide gate of the known TFT ha s a dielectric constant of 3.9. The amount of charge induced in the channel is proportional to this number. The gain obtained due to the gate""s dielectric constant is countered by the Miller capacitance which makes the gate more difficult to drive. These effects exactly cancel.
There is, however, a benefit in use of a high dielectric constant material to isolate the gate, since it can allow a reduction in the threshold voltage of the transistor. The threshold voltage is the gate voltage required to turn on a channel. It is non-zero due to the undesirable effects of fixed charge in the oxide and any work function difference across the dielectric due to the materials used. These may serve to reduce threshold voltage for some kinds of devices.
There is a third effect, due to interface trapping levels, which always increases threshold voltage. This effect is very important in polymers so that there is great benefit in having a high gate dielectric constant.
Dielectric constant can vary from 1 to several hundred, but for most materials suitable for use in TFTs it is typically in the range 3 to 25. These are most likely to be the oxides of metals.
A major application of thin film polymer transistors is in flat panel displays. They are required to be very large in area so that the use of silicon is usually not feasible, and even if large area silicon were available the cost would be prohibitive. For most display applications the substrate material has to be transparent, making glass or plastic the favoured choice. There is therefore a need to limit the temperatures involved in manufacture to be compatible with such substrates. It is desirable that these temperatures should not be substantially greater than 200 C.
Efforts to reduce Miller capacitance have been limited by the dimensional tolerances in the processes used to fabricate horizontal component structures. In the known TFT, the gate and the source/drain are formed as successive layers using photolithographic techniques involving correspondingly formed resist layers, a first layer being used to form the gate and a further layer to form the source/drain. The accuracy of the relative lateral positioning of the gate and the source/drain is thus limited by tolerances in the formation of the resist layers themselves.
Hence a first object of the present invention is to make possible a method of electronic component fabrication having improved relative lateral positioning of two or more parts of the component.
The improvement is not only desirable in transistor manufacture but offers particular benefits in this area.
An additional or alternative object of the present invention is to make possible a transistor having reduced overlap capacitance.
An additional or alternative object of the present invention is to make possible a transistor having a high gate dielectric constant and particularly a gate dielectric constant higher than that of silicon dioxide. It is particularly desired to enable such a transistor to be fabricated without use of excessive temperatures.
It is further desired to achieve one or more of the above objects using a polymer based transistor, most preferably a thin film transistor.
In accordance with a first aspect of the present invention there is a method of electronic component fabrication comprising providing an electrically conductive layer upon a substrate; providing a mask over the electrically conductive layer, the mask having at least one window; etching the conductive layer through the window to form an opening in the conductive layer, and depositing conductive material through the window to form an island in the opening, the etching being carried out such that the conductive layer is undercut at the periphery of the window so that the periphery of the island is spaced apart from the periphery of the opening.
By using the same mask window in forming the opening in the conductive layer and the island it becomes possible to determine the relative positioning of these two items with greatly improved accuracy not limited by the tolerance involved in manufacture of the mask itself. The undercutting of the conductive layer, which may for example result from use of a chemical etching process, is typically regarded as a problematic phenomenon, but is used to advantage in the method according to the present invention and makes it possible to ensure that despite being formed using a common mask the items are separated spatially - and if necessary also isolated electronically. Requiring only a single mask for fabrication of two or more parts, the fabrication process according to the present invention is straightforward. Where the process is applied to transistor manufacture the island may form a transistor gate while separate portions of the conductive layer form the transistor source and drain. Gate isolation is, in a particularly preferred method according to the present invention, provided for by selectively anodising the gate.
A metal gate is particularly preferred. Aluminum is a suitable material. The fabrication process can be carried out without excessively high temperatures and the resulting dielectric (metal oxide) layer can have the desired high dielectric constant.
Formation of the island is, in an especially preferred method according to the present invention, carried out by metal evaporation. The process can form an island whose periphery closely matches the periphery of the window.
In a particularly preferred method according to the present invention the transistor body is formed by introducing semiconductor material into the space between the island and the conductive layer. It is particularly preferred that the semiconductor materials comprises a polymer material. A suitable material is regio-regular polyalkylthiophene, although other polythiophenes are also suitable.
It is to be understood that the term xe2x80x9cpolymerxe2x80x9d as used herein includes, as well as longer chain polymers, the relatively short chain oligomers.
In accordance with a second aspect of the present invention there is a transistor comprising a source and a drain both substantially co-planar with and laterally separated from a gate, and a body comprising semiconductor material disposed between the source/drain and the gate.
The source/drain and the gate may be co-planar in the sense that they are formed upon a common substrate.
It is especially preferred that the source/drain and the gate are formed using a common mask having a window, one being formed by etching through the window such as to undercut at the window periphery and the other being formed by deposition of material through the window.
The gate may be insulated from the body by a dielectric layer formed thereupon by selective anodisation